1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly to a shift register circuit used as a scanning-line driving circuit in an image display apparatus, or the like, which is formed only of field effect transistors of the same conductivity type.
2. Description of the Background Art
In an image display apparatus (hereinafter, referred to as “display apparatus”) such as a liquid crystal display, a plurality of pixels are arranged in a matrix in a display panel and a gate line (scanning line) is provided for each row of pixels (pixel line) in the display panel. In a cycle of one horizontal period of a display signal, the gate lines are sequentially selected and driven, to update a displayed image. As a gate line driving circuit (scanning-line driving circuit) for sequentially selecting and driving the pixel lines, i.e., the gate lines, a shift register may be used, which performs a round of shift operation in one frame period of the display signal.
In order to reduce the number of steps in a manufacturing process for a display apparatus, it is preferable that the shift register used as the gate line driving circuit should be formed only of field effect transistors of the same conductivity type. Therefore, various types of shift registers formed only of N-type or P-type field effect transistors and display apparatuses containing such shift registers have been proposed (e.g., Japanese Patent Application Laid Open Gazette Nos. 2004-78172 and 8-87897 (Patent Documents 1 and 2)). As a field effect transistor, a MOS (Metal Oxide Semiconductor) transistor, a TFT (Thin Film Transistor) or the like is used.
Other references are Japanese Patent Application Laid Open Gazette Nos. 10-500243, 2001-52494 and 2002-133890 (Patent Documents 3, 4 and 5).
A shift register as a gate line driving circuit consists of a plurality of cascaded shift register circuits each of which is provided for one pixel line, i.e., one gate line. In this specification, for simple discussion, each of a plurality of shift register circuits which form a gate line driving circuit is referred to as a “unit shift register”.
In a background-art gate line driving circuit, unit shift registers are connected in cascade with an output terminal of each unit shift register is connected to an input terminal of its succeeding-stage unit shift register. Specifically, a unit shift register needs to drive not only a gate line but also the succeeding-stage unit shift register by using an output signal, and therefore, to an output terminal of each unit shift register, both the gate line which is thereby driven and an input terminal of the succeeding-stage unit shift register are connected (see, e.g., FIG. 5 of Patent Document 1). With this constitution, however, a load on the gate line exerts an influence upon the input terminal of the succeeding-stage unit shift register, to thereby cause a delay in an output signal. The signal delay increases as the stage becomes posterior in the cascade connection, and sometimes, this eventually causes a problem in display.
On the other hand, a unit shift register shown in FIG. 12 of Patent Document 1 has a constitution in which an output signal (gate line driving signal) for driving a gate line and an output signal (carry signal) for driving the succeeding-stage unit shift register are outputted from individual output terminals by using individual transistors. This reduces an influence that the load on the gate line exerts upon an input terminal of the succeeding-stage unit shift register and therefore alleviates the above problem.
In the unit shift register of Patent Document 1, though a transistor (transistor M1 in FIG. 12 of Patent Document 1) for activating a gate line driving signal and a transistor (transistor TR1 in the same figure) for activating a carry signal are separately provided, gates (control electrodes) of these two transistors are connected to the same node (node N1 of the same figure). The gate of the transistor for activating the gate line driving signal is stepped up at the rise of the gate line driving signal by the coupling of gate-channel capacitance of the transistor and a capacitive element (capacitor C of the same figure) connected between a gate and a source of the transistor. Therefore, in the shift register of Patent Document 1, a gate of the transistor for activating the carry signal is also stepped up at the rise of the gate line driving signal. As a result, an influence of the gate line driving signal is exerted upon the carry signal.
For this reason, when the rising speed of the gate line driving signal becomes lower due to variations in ambient temperature, threshold voltage of a transistor or the like, the rising speed of the carry signal accordingly becomes lower and this disadvantageously makes it difficult to perform a high-speed operation.